Application Cases

Experiment Name: Separation of HeLa Cells Using Dielectrophoresis Chips

Research Direction: Dielectrophoresis

Testing Equipment: Signal generator, ATA-2021B high-voltage amplifier, oscilloscope, microscope, microfluidic chip, syringe pump.

Experimental Procedure:

Figure: Experimental Block Diagram

The concentration of HeLa cells used in the experiment was 3e6 cells per milliliter. The sample injection flow rates were 0.08 ml/h, 0.10 ml/h, and 0.12 ml/h. The applied excitation voltages were 11 Vpp, 13 Vpp, and 15 Vpp, with a frequency of 600 kHz. The chip performance was still analyzed based on cell separation efficiency. Additionally, the data statistics method was the same as in the previous section. To investigate the improvement in separation efficiency of the two-stage chip compared to the single-stage chip under the same conditions, data were also collected from the first stage of the two-stage chip, using the same statistical method as for the second stage. High-speed microscopic cameras were used to capture phenomena at the outlets of the first and second stages, as shown in the figure below.

Figure: nDEP Phenomenon Diagram of the Two-Stage Structure

Experimental Results:

As shown in the figure above, the phenomenon diagram was captured under a sample injection flow rate of 0.08 ml/h. (a) shows the upstream part of the first-stage outlet. After applying the electric field, most cells were polarized and repelled to the lower sides. However, due to the high cell density and relatively fast flow rate, the Stokes force played a dominant role, causing many cells to continue moving in the middle part of the channel. (b) shows the first-stage outlet. It can be observed that most cells were expelled from the side outlets under the influence of negative dielectrophoresis (nDEP) force. Nevertheless, many cells still escaped from the middle outlet under the guidance of Stokes drag force and entered the second stage.

(c) shows the separation situation upstream of the second stage. After separation by the first stage, the cell concentration decreased significantly, and the flow rate was reduced to one-third of the original. This is because, with the sample injection flow rate unchanged, the volumetric flow rate decreased to one-third after passing through the first-stage outlet. The reduced flow rate significantly diminished the Stokes drag force exerted by the fluid on the cells, allowing the nDEP force to dominate. The vast majority of cells were rapidly repelled to the lower sidewalls, as shown in (c). Figure (d) shows the phenomenon at the second-stage outlet. It can be seen that almost most cells adhered to the walls and were discharged from the lower side outlets. Simultaneously, the separation efficiencies at the first-stage outlet and the second-stage outlet were statistically analyzed, as shown in the following two figures.

Figure: First-Stage Outlet Separation Efficiency

As shown in the figure above, compared to the single-stage chip, the cell enrichment efficiency increased with increasing voltage and decreasing flow rate. Under a constant applied voltage, the separation efficiency decreased as the flow rate increased. At 15 Vpp and a flow rate of 0.08 ml/h, the separation efficiency was 82.2%. When the flow rate was increased to 0.12 ml/h, the separation efficiency was 74.9%. When the voltage was reduced to 11 Vpp, the separation efficiency was 69.6%. It can be seen that achieving the ideal separation effect solely through first-stage separation is challenging. Subsequently, the enrichment efficiency of the second stage was statistically analyzed.

The figure below indicates that at a flow rate of 0.08 ml/h, the separation efficiency of the second stage reached 93.7%. At a flow rate of 0.1 ml/h, the efficiency could still reach 91.7%. It can be observed that compared to the single-stage chip, the separation efficiency remained above 90% even when the flow rate was increased by a factor of 2.5. Additionally, the cell concentration in the two-stage chip experiment was increased by a factor of 5. Therefore, the cascaded design of this chip can enhance its working performance.

Figure: Second-Stage Outlet Separation Efficiency

Figure: ATA-2021B High-Voltage Amplifier Specifications and Parameters